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MC14099B 8-Bit Addressable Latches
The MC14099B is an 8-bit addressable latch. Data is entered in serial form when the appropriate latch is addressed (via address pins A0, A1, A2) and write disable is in the low state. For the MC14099B the input is a unidirectional write only port. The data is presented in parallel at the output of the eight latches independently of the state of Write Disable, Write/Read or Chip Enable. A Master Reset capability is available on both parts.
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16 PDIP-16 P SUFFIX CASE 648 MC14099BCP AWLYYWW 1 16 SOIC-16 DW SUFFIX CASE 751G 1 14099B
* * * * * *
Serial Data Input Parallel Output Master Reset Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low-power TTL Loads or One Low-Power Schottky TTL Load over the Rated Temperature Range MC14099B pin for pin compatible with CD4099B
AWLYYWW
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value - 0.5 to +18.0 - 0.5 to VDD + 0.5 10 500 - 55 to +125 - 65 to +150 260 Unit V V mA mW C C C SOEIAJ-16 F SUFFIX CASE 966
16 MC14099B AWLYWW 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week
ORDERING INFORMATION
Device MC14099BCP MC14099BDW MC14099BDWR2 MC14099BF MC14099BFEL Package PDIP-16 SOIC-16 SOIC-16 SOEIAJ-16 SOEIAJ-16 Shipping 2000/Box 2350/Box 1000/Tape & Reel See Note 1. See Note 1.
2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
v
v
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
(c) Semiconductor Components Industries, LLC, 2000
1
March, 2000 - Rev. 3
Publication Order Number: MC14099B/D
MC14099B
PIN ASSIGNMENT
Q7 RESET DATA WRITE DISABLE A0 A1 A2 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q6 Q5 Q4 Q3 Q2 Q1 Q0
WRITE DISABLE DATA A0 A1 A2 RESET 5 6 DECODER 7 VDD = 16 VSS = 8
MC14099B
4 3 8 9 10 11 12 8 13 LATCHES 14 15 1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 15 -- -- Min -- -- -- - 55_C 25_C 125_C Max Min -- -- -- Typ (4.) 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 -- -- -- "1" Level VOH Vin = 0 or VDD 4.95 9.95 14.95 -- -- -- 4.95 9.95 14.95 -- -- -- 5.0 10 15 4.95 9.95 14.95 -- -- -- Vdc Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) VIL Vdc 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- 2.25 4.50 6.75 2.75 5.50 8.25 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- VIH Vdc 3.5 7.0 11 3.5 7.0 11 3.5 7.0 11 Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) IOH mAdc Source - 3.0 - 0.64 - 1.6 - 4.2 0.64 1.6 4.2 -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 0.51 1.3 3.4 -- -- -- - 4.2 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 - 1.7 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 -- -- -- Sink IOL mAdc Input Current Iin 0.1 -- -- 0.00001 5.0 15 0.1 7.5 1.0 -- -- Adc pF pF Input Capacitance (Vin = 0) Cin Cin Input Capacitance MC14599B -- Data (pin 3) (Vin = 0) Quiescent Current (Per Package) 22.5 IDD 5.0 10 15 5.0 10 15 -- -- -- 5.0 10 20 -- -- -- 0.005 0.010 0.015 5.0 10 20 -- -- -- 150 300 600 Adc Total Supply Current (5.) (6.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT IT = (1.5 A/kHz) f + IDD IT = (3.0 A/kHz) f + IDD IT = (4.5 A/kHz) f + IDD Adc 4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 5. The formulas given are for the typical characteristics only at 25_C. 6. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.004.
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7. The formulas given are for the typical characteristics only at 25_C. 8. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
Removal Time Write Disable to Address
Set Up Time Address to Write Disable
Hold Time Write Disable to Data
Set Up Time Data to Write Disable
Write Disable
Pulse Widths Reset
Propagation Delay Time, MC14599B only Chip Enable, Write/Read to Data
Propagation Delay Time Data to Output Q
Output Rise and Fall Time tTLH, tTHL = (1.35 ns/pF) CL + 32 ns tTLH, tTHL = (0.6 ns/pF) CL + 20 ns tTLH, tTHL = (0.4 ns/pF) CL + 20 ns
Address to Data
CE to Output Q (MC14599B only)
Reset to Output Q
Write Disable to Output Q
Characteristic
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Symbol
MC14099B
tPHL, tPLH
tPHL, tPLH
tTLH, tTHL
tw(H) tw(L)
trem
tsu
tsu
th
3 VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min 100 80 40 150 75 50 100 50 35 320 160 120 150 75 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 0 Typ (8.) - 80 - 40 - 40 160 80 60 200 90 75 200 80 65 225 100 75 175 80 65 200 80 60 200 75 50 100 50 40 45 30 10 75 40 25 50 25 20 75 40 25 Max 400 180 150 400 160 130 450 200 150 350 160 130 400 160 120 400 150 100 200 100 80 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
MC14099B
MC14099B FUNCTION DIAGRAM
RESET 2 9 Q0 DATA 3
WRITE 4 DISABLE TO OTHER LATCHES
EACH LATCH
ZERO SELECT 10 Q1 11 Q2 12 Q3
A0 5
A1 6
ADDRESS DECODER
OTHER LATCHES
13 Q4 14 Q5
A2 7 (M.S.B.)
15 Q6 1 Q7
TRUTH TABLE
Write Disable 0 0 1 1 Reset 0 1 0 1 Addressed Latch Data Data Qn* Reset Unaddressed Latches Qn* Reset { Qn* Reset CAUTION: To avoid unintentional data changes in the latches, Write Disable must be active (high) during transitions on the address inputs A0, A1, and A2.
*Qn is previous state of latch. Reset to zero state.
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MC14099B
SWITCHING WAVEFORMS
VDD DATA OR WRITE DISABLE 50% VSS tPLH 90% 50% 10% tTLH tTHL WRITE DISABLE 50% VSS tsu VDD RESET 50% VSS tPHL DATA 50% VSS th VDD tPHL ADDRESS 50% VSS tsu tw(L) trem VDD VDD
OUTPUT Q
tw(H)
OUTPUT Q
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MC14099B
PACKAGE DIMENSIONS
-A-
16 9
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
SOIC-16 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G-03 ISSUE B
D
16 M 9
A
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
B
1
8
16X
B TA
S
B B
S
h X 45 _
M
8X
0.25
E
0.25
M
A1
14X
e
SEATING PLANE
DIM A A1 B C D E e H h L
A
L
T
C
q
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MC14099B
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O
LE Q1 E HE
1 8
16
9
M_ L DETAIL P
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC14099B
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PUBLICATION ORDERING INFORMATION
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MC14099B/D

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